Implementation of High-Order Convolution Algorithms with Low Latency on Silicon Chips

Anderegg R, Felber N, Fichtner W, Franke U. Implementation of High-Order Convolution Algorithms with Low Latency on Silicon Chips. In: AES Convention 117. Audio Engineering Society; 2004. Paper 6304. Available from: https://aes.org/publications/elibrary-page/?id=12961

@inproceedings{Anderegg2004_12961,
  author = {Anderegg, Rolf and Felber, Norbert and Fichtner, Wolfgang and Franke, Ulrich},
  title = {{Implementation of High-Order Convolution Algorithms with Low Latency on Silicon Chips}},
  booktitle = {AES Convention 117},
  note = {Paper 6304},
  year = {2004},
  month = oct,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=12961}
}

TY  - CPAPER
TI  - Implementation of High-Order Convolution Algorithms with Low Latency on Silicon Chips
AU  - Anderegg, Rolf
AU  - Felber, Norbert
AU  - Fichtner, Wolfgang
AU  - Franke, Ulrich
T2  - AES Convention 117
M1  - Paper 6304
PY  - 2004
DA  - 2004/10/06
UR  - https://aes.org/publications/elibrary-page/?id=12961
PB  - Audio Engineering Society
LA  - en
AB  - Audio signal processing often requires modeling of large rooms (e.g. churches) with impulse responses of several seconds duration. Direct convolution of the sound stream with such long responses exceeds the capacity of common signal processors by far. Using the Fast Fourier Transform instead reduces the number of operations logarithmically, but introduces unacceptable latency. Segmenting the processing into initial short blocks and subsequent longer ones lets one trade latency vs. computation power as presented in previous AES papers. Hardware-wise the reduction of operations comes at the cost of large storage with high memory bandwidths. Dedicated application specific integrated circuits (ASIC) are predestined to perform the rather regular processing, freeing the processors for other tasks. This paper shows suitable architectures for integration on silicon of optimized fast-convolution algorithms. Possible optimizations for fast-convolution algorithms are examined. Based on these findings different architectures for integration on ASIC/FPGA (Field Programmable Gate Array) of such algorithms are developed, analysed and compared. The paper is concluded by presenting an exemplary ASIC implementation.
ER  -