VLSI Implementation of a Fully Digital Asynchronous Audio Sample-Rate Converter

Rothacher F, Felber N. VLSI Implementation of a Fully Digital Asynchronous Audio Sample-Rate Converter. In: AES Convention 96. Audio Engineering Society; 1994. Paper 3832. Available from: https://aes.org/publications/elibrary-page/?id=6400

@inproceedings{Rothacher1994_6400,
  author = {Rothacher, Fritz and Felber, Norbert},
  title = {{VLSI Implementation of a Fully Digital Asynchronous Audio Sample-Rate Converter}},
  booktitle = {AES Convention 96},
  note = {Paper 3832},
  year = {1994},
  month = feb,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=6400}
}

TY  - CPAPER
TI  - VLSI Implementation of a Fully Digital Asynchronous Audio Sample-Rate Converter
AU  - Rothacher, Fritz
AU  - Felber, Norbert
T2  - AES Convention 96
M1  - Paper 3832
PY  - 1994
DA  - 1994/02/06
UR  - https://aes.org/publications/elibrary-page/?id=6400
PB  - Audio Engineering Society
LA  - en
AB  - A VLSI circuit is presented that performs sampling rate conversion of digital stereo audio signals. Conceptually, the converter interpolates to 4 Ghz, and then decimates to the desired output sampling rate. The chip is intended for 18-bit professional audio applications with arbitrarily varying input and output sampling frequencies from 25 to 70 kHz. Out chip is compared in architecture and performance to the commercial realization presented in (2) (Analog Devices AD1890).
ER  -