Area Efficient Decimation Filter for an 18-Bit Delta-Sigma Analog-to-Digital Converter

Lin K, Paulos J. Area Efficient Decimation Filter for an 18-Bit Delta-Sigma Analog-to-Digital Converter. In: AES Convention 98. Audio Engineering Society; 1995. Paper 3989. Available from: https://aes.org/publications/elibrary-page/?id=7777

@inproceedings{Lin1995_7777,
  author = {Lin, Kun and Paulos, John},
  title = {{Area Efficient Decimation Filter for an 18-Bit Delta-Sigma Analog-to-Digital Converter}},
  booktitle = {AES Convention 98},
  note = {Paper 3989},
  year = {1995},
  month = feb,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=7777}
}

TY  - CPAPER
TI  - Area Efficient Decimation Filter for an 18-Bit Delta-Sigma Analog-to-Digital Converter
AU  - Lin, Kun
AU  - Paulos, John
T2  - AES Convention 98
M1  - Paper 3989
PY  - 1995
DA  - 1995/02/06
UR  - https://aes.org/publications/elibrary-page/?id=7777
PB  - Audio Engineering Society
LA  - en
AB  - The paper describes a multistage decimation filter which consists of seven-cascaded comb filters and a 50-tap single-stage finite-impulse response filter. A novel, multirate comb filter structure is used to reduce the date path width. The coefficients of the FIR filter are optimally quanticized to canonical-signed-digit form to realize a multiplier-free (shift-and-add) implementation with a single accumulator and a 256Fs master clock.
ER  -