Analysis of Jitter Rejection of SRCs and DACs Using an NCO

Wood M. Analysis of Jitter Rejection of SRCs and DACs Using an NCO. In: AES Convention 100. Audio Engineering Society; 1996. Paper 4261. Available from: https://aes.org/publications/elibrary-page/?id=7515

@inproceedings{Wood1996_7515,
  author = {Wood, M.},
  title = {{Analysis of Jitter Rejection of SRCs and DACs Using an NCO}},
  booktitle = {AES Convention 100},
  note = {Paper 4261},
  year = {1996},
  month = may,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=7515}
}

TY  - CPAPER
TI  - Analysis of Jitter Rejection of SRCs and DACs Using an NCO
AU  - Wood, M.
T2  - AES Convention 100
M1  - Paper 4261
PY  - 1996
DA  - 1996/05/06
UR  - https://aes.org/publications/elibrary-page/?id=7515
PB  - Audio Engineering Society
LA  - en
AB  - Some recent sample-rate converters (SRCs) and digital-to-analog converters (DACs) have included circuitry which rejects jitter on the applied word clock signals. Jitter attenuation can lead to audible improvements in the playback material, especially when the word clock is synthesized from a highly jittered recovered clock, such as in DBS systems. A simple numerically controlled oscillator (NCO) digital circuit is presented which can be used to demonstrate the jitter rejection. Results are reviewed.
ER  -