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Convention Paper

DSP Strategies for Faster Polynomial Interpllation

Authors: Wise, Duane K.; Barish, Jeffrey; Lindemann, Eric

AES Convention 101 · Paper 4370 · November 1996

Abstract

An algorithm for calculating a real-time sampling-rate conversion via low-order polynomial interpolation of a digital signal is described. Modifications to common DSP chip architectures are then suggested which will reduce the computational complexity of the presented algorithm compared to that of the classical algorithm.

Details

Published in
AES Convention 101
AES Convention
101
Paper number
4370
Publication date
November 6, 1996
Session subject
Signal Processing
Affiliation
EuPhonics, Inc., Boulder, CO (See document for exact affiliation information.)
Type
Convention Paper