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Convention Paper

VHDL Implementations of Integer Noise Shapers with Floating-Point Accuracy

Authors: Clark, I. G.; Hiorns, R. E.; Davies, A. C.

AES Convention 94 · Paper 3568 · March 1993

Abstract

This paper examines methods of hardware implementation for integer noise shaping using VHDL (the newly recognized standard for hardware description). Methods of integer coefficient calculation will be discussed for accuracy near floating point. The technique reduces the calculation complexity with a view to reducing the silicon area for hardware implementation, while maintaining 24-bit quality in a minimally oversampled output. Performance will be demonstrated using computer simulation. (VHDL: Very high-speed integrated-circuit hardware description language.)

Details

Published in
AES Convention 94
AES Convention
94
Paper number
3568
Publication date
March 6, 1993
Session subject
Digital Signal Processing
Affiliation
University of London, Department of Electronic and Electrical Engineering, London, United Kingdom (See document for exact affiliation information.)
Type
Convention Paper