Field-Programmable Gate-Array-Based 32-Times Oversampling Eighth-Order Sigma-Delta Audio DAC

Risbo L. Field-Programmable Gate-Array-Based 32-Times Oversampling Eighth-Order Sigma-Delta Audio DAC. In: AES Convention 96. Audio Engineering Society; 1994. Paper 3808. Available from: https://aes.org/publications/elibrary-page/?id=6424

@inproceedings{Risbo1994_6424,
  author = {Risbo, Lars},
  title = {{Field-Programmable Gate-Array-Based 32-Times Oversampling Eighth-Order Sigma-Delta Audio DAC}},
  booktitle = {AES Convention 96},
  note = {Paper 3808},
  year = {1994},
  month = feb,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=6424}
}

TY  - CPAPER
TI  - Field-Programmable Gate-Array-Based 32-Times Oversampling Eighth-Order Sigma-Delta Audio DAC
AU  - Risbo, Lars
T2  - AES Convention 96
M1  - Paper 3808
PY  - 1994
DA  - 1994/02/06
UR  - https://aes.org/publications/elibrary-page/?id=6424
PB  - Audio Engineering Society
LA  - en
AB  - A novel Sigma-Delta based audio DAC system is presented. The converter operates at only 32-times oversampling (1.4 MHz) and uses an eighth-order Sigma-Delta modulator implemented in a single FPGA circuit. Two different DAC circuits have been implemented: One using switched capacitor charge packets and one using nonreturn to zero pulses. A voltage-controlled Xtal oscillator-based PLL ensures low-jitter sampling clock recovery.
ER  -