Design of Audio Processing Systems with Autogenerated User Interfaces for System-on-Chip Field Programmable Gate Arrays

Vannoy T, Wickham D, Sobrero D, Dack C, Snider R, Davis T. Design of Audio Processing Systems with Autogenerated User Interfaces for System-on-Chip Field Programmable Gate Arrays. In: AES Convention 149. Audio Engineering Society; 2020. Paper 10428. Available from: https://aes.org/publications/elibrary-page/?id=20965

@inproceedings{Vannoy2020_20965,
  author = {Vannoy, Trevor and Wickham, Dylan and Sobrero, Dustin and Dack, Connor and Snider, Ross and Davis, Tyler},
  title = {{Design of Audio Processing Systems with Autogenerated User Interfaces for System-on-Chip Field Programmable Gate Arrays}},
  booktitle = {AES Convention 149},
  note = {Paper 10428},
  year = {2020},
  month = oct,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=20965}
}

TY  - CPAPER
TI  - Design of Audio Processing Systems with Autogenerated User Interfaces for System-on-Chip Field Programmable Gate Arrays
AU  - Vannoy, Trevor
AU  - Wickham, Dylan
AU  - Sobrero, Dustin
AU  - Dack, Connor
AU  - Snider, Ross
AU  - Davis, Tyler
T2  - AES Convention 149
M1  - Paper 10428
PY  - 2020
DA  - 2020/10/06
UR  - https://aes.org/publications/elibrary-page/?id=20965
PB  - Audio Engineering Society
LA  - en
AB  - System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) are well-suited for real time audio processing because of their high performance and low latency. However, interacting with FPGAs at runtime is complex and difficult to implement, which limits their adoption in real-world applications. We present an open source software stack that makes creating interactive audio processing systems on SoC FPGAs easier. The software stack contains a web app with an autogenerated graphical user interface, a proxy server, a deployment manager, and device drivers. An example design comprising custom audio hardware, a delay and sum beamformer, an amplifier, filters, and noise suppression is presented to demonstrate our software. This example design provides a reference that other developers can use to create high performance interactive designs that leverage the processing power of FPGAs.
ER  -