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Convention Paper

A High Performance S/PDIF Receiver

Authors: Lesso, Paul

AES Convention 121 · Paper 6948 · October 2006

Abstract

This paper details the design and implementation of a novel S/PDIF transceiver with a very low jitter bandwidth. We describe and demonstrate a system based on multiple-loops that synchronises to the incoming data stream with a very low bandwidth and provides the original data unmodified on a clean low jitter output clock without the need for a sample rate converter. Thus we eliminate any jitter above a low frequency (typically 10Hz) on the input data and also avoid any distortion caused by sample rate converters.

Details

Published in
AES Convention 121
AES Convention
121
Paper number
6948
Publication date
October 6, 2006
Session subject
Amplifiers & High Resolution
Affiliation
Wolfson Microelectronics (See document for exact affiliation information.)
Type
Convention Paper