P. Andreani, F. Nyboe, and L. Risbo, “Time Domain Analysis of Open Loop Distortion in Class D Amplifier Output Stages,” in Proc. AES Conference: 27th International Conference: Efficient Audio Power Amplification, Sep. 2005, Paper 4-3. [Online]. Available: https://aes.org/publications/elibrary-page/?id=13274
Andreani P, Nyboe F, Risbo L. Time Domain Analysis of Open Loop Distortion in Class D Amplifier Output Stages. In: AES Conference: 27th International Conference: Efficient Audio Power Amplification. Audio Engineering Society; 2005. Paper 4-3. Available from: https://aes.org/publications/elibrary-page/?id=13274
@inproceedings{Andreani2005_13274,
author = {Andreani, Pietro and Nyboe, Flemming and Risbo, Lars},
title = {{Time Domain Analysis of Open Loop Distortion in Class D Amplifier Output Stages}},
booktitle = {AES Conference: 27th International Conference: Efficient Audio Power Amplification},
note = {Paper 4-3},
year = {2005},
month = sep,
publisher = {Audio Engineering Society},
url = {https://aes.org/publications/elibrary-page/?id=13274}
}
TY - CPAPER
TI - Time Domain Analysis of Open Loop Distortion in Class D Amplifier Output Stages
AU - Andreani, Pietro
AU - Nyboe, Flemming
AU - Risbo, Lars
T2 - AES Conference: 27th International Conference: Efficient Audio Power Amplification
M1 - Paper 4-3
PY - 2005
DA - 2005/09/06
UR - https://aes.org/publications/elibrary-page/?id=13274
PB - Audio Engineering Society
LA - en
AB - During the long history of Class AB amplifiers, many topology improvements have been developed with the aim of reducing open-loop THD. As Class D amplifiers become widely used, a new learning of such improvements is needed, since the basic distortion mechanisms are very different from those of Class AB amplifiers. This is even more important with Class D designs because the very high feedback loop gains seen in Class AB designs is not always achievable in Class D designs, and in some cases no feedback is used at all, because it cannot easily be applied to digital input systems at low cost. This paper analyzes the nature of different contributors to THD in Class D output stages. It is shown how large-signal transfer characteristic analysis can be applied to individual parts of a PWM output signal, to help identify problems and optimize a design for minimum THD.
ER -