Integrated Stereo Sigma-Delta Class D Amplifier

Adams R, Gaalaas E, Liu BY, Morajkar R, Nishimura N, Sweetland K. Integrated Stereo Sigma-Delta Class D Amplifier. In: AES Convention 118. Audio Engineering Society; 2005. Paper 6452. Available from: https://aes.org/publications/elibrary-page/?id=13168

@inproceedings{Adams2005_13168,
  author = {Adams, Robert and Gaalaas, Eric and Liu, Bill Yang and Morajkar, Rajeev and Nishimura, Naoaki and Sweetland, Karl},
  title = {{Integrated Stereo Sigma-Delta Class D Amplifier}},
  booktitle = {AES Convention 118},
  note = {Paper 6452},
  year = {2005},
  month = may,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=13168}
}

TY  - CPAPER
TI  - Integrated Stereo Sigma-Delta Class D Amplifier
AU  - Adams, Robert
AU  - Gaalaas, Eric
AU  - Liu, Bill Yang
AU  - Morajkar, Rajeev
AU  - Nishimura, Naoaki
AU  - Sweetland, Karl
T2  - AES Convention 118
M1  - Paper 6452
PY  - 2005
DA  - 2005/05/06
UR  - https://aes.org/publications/elibrary-page/?id=13168
PB  - Audio Engineering Society
LA  - en
AB  - A 2x40W integrated stereo sigma-delta class D amplifier with 100 dB SNR is realized in 0.6um BCDMOS technology. Feedback from power stage outputs gives 0.001% THD and 65dB PSRR. Modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak related to the hysteresis, but is otherwise tone-free, unlike PWM modulators which contain many harmonics of the PWM clock frequency.
ER  -