Performance Improvements for Audio Algorithms that Use Non-sequential Memory Accesses on Digital Signal Processors

Watson MA, Ganju V, Maur G. Performance Improvements for Audio Algorithms that Use Non-sequential Memory Accesses on Digital Signal Processors. In: AES Convention 116. Audio Engineering Society; 2004. Paper 6090. Available from: https://aes.org/publications/elibrary-page/?id=12729

@inproceedings{Watson2004_12729,
  author = {Watson, Matthew A. and Ganju, Vineet and Maur, Gaganjot},
  title = {{Performance Improvements for Audio Algorithms that Use Non-sequential Memory Accesses on Digital Signal Processors}},
  booktitle = {AES Convention 116},
  note = {Paper 6090},
  year = {2004},
  month = may,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=12729}
}

TY  - CPAPER
TI  - Performance Improvements for Audio Algorithms that Use Non-sequential Memory Accesses on Digital Signal Processors
AU  - Watson, Matthew A.
AU  - Ganju, Vineet
AU  - Maur, Gaganjot
T2  - AES Convention 116
M1  - Paper 6090
PY  - 2004
DA  - 2004/05/06
UR  - https://aes.org/publications/elibrary-page/?id=12729
PB  - Audio Engineering Society
LA  - en
AB  - Many audio algorithms, such as room simulators and reverberators, operating on Digital Signal Processors access large delay buffers in a non-sequential fashion. Generally, these delay buffers are too large to reside in the on-chip memory of the processor, so they must be placed in external, slow memories. Furthermore, the non-sequential accesses present a problem for maintaining high performance. This paper presents a number of methods that may be employed to improve the performance of the memory accesses of such algorithms. Methods examined include the use of direct CPU memory access, hardware data cache, and dedicated Direct Memory Access (DMA) controllers. Additionally, the algorithm, sample block size, delay taps, tap spacing, and buffer size will be examined and performance results will be presented.
ER  -