A Gate-Array Multiplier for Digital Audio Processing

Moorer JA, Borish J, Snell J. A Gate-Array Multiplier for Digital Audio Processing. In: AES Convention 78. Audio Engineering Society; 1985. Paper 2243. Available from: https://aes.org/publications/elibrary-page/?id=11512

@inproceedings{Moorer1985_11512,
  author = {Moorer, James A. and Borish, Jeffrey and Snell, John},
  title = {{A Gate-Array Multiplier for Digital Audio Processing}},
  booktitle = {AES Convention 78},
  note = {Paper 2243},
  year = {1985},
  month = may,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=11512}
}

TY  - CPAPER
TI  - A Gate-Array Multiplier for Digital Audio Processing
AU  - Moorer, James A.
AU  - Borish, Jeffrey
AU  - Snell, John
T2  - AES Convention 78
M1  - Paper 2243
PY  - 1985
DA  - 1985/05/06
UR  - https://aes.org/publications/elibrary-page/?id=11512
PB  - Audio Engineering Society
LA  - en
AB  - Processing of digital audio requires extremely high-speed arithmetic operations to be performed. Although the audio samples themselves are 16 bits due to AD and DA converter limitations, 24 bits or more are required for intermediate values and for filter coefficients. There are no commercial integrated circuits of the required speed and width at the current time, although there are many on the horizon. We have designed and had made a pair of gate arrays that realize a 24 bit by 24 bit multiply, followed by a 56-bit accumulator with optional saturation. The circuits utilize a 4-stage pipeline and operate with a 65 nanosecond clock. This allows multiply/accumulate operations to be started at a rate greater than 15 Mhz. The circuits have internal diagnostic paths built-in, so that all pipeline stages may be read out.
ER  -