Configurable Microprocessor Implementation of Low Bit Rate Audio Decoding

Brown GS. Configurable Microprocessor Implementation of Low Bit Rate Audio Decoding. In: AES Convention 113. Audio Engineering Society; 2002. Paper 5689. Available from: https://aes.org/publications/elibrary-page/?id=11268

@inproceedings{Brown2002_11268,
  author = {Brown, Gary S.},
  title = {{Configurable Microprocessor Implementation of Low Bit Rate Audio Decoding}},
  booktitle = {AES Convention 113},
  note = {Paper 5689},
  year = {2002},
  month = oct,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=11268}
}

TY  - CPAPER
TI  - Configurable Microprocessor Implementation of Low Bit Rate Audio Decoding
AU  - Brown, Gary S.
T2  - AES Convention 113
M1  - Paper 5689
PY  - 2002
DA  - 2002/10/06
UR  - https://aes.org/publications/elibrary-page/?id=11268
PB  - Audio Engineering Society
LA  - en
AB  - Using a configurable microprocessor to implement low-bit-rate audio applications by tailoring the instruction set reduces algorithm complexity and implementation cost. As an example, this paper describes a Dolby Digital (AC-3) decoder implementation that uses a commercially-available configurable microprocessor to achieve 32-bit floating-point precision while minimizing the required processor clock rate and die size. This paper focuses on how the audio quality and features of the reference decoder algorithm dictate the customization of the microprocessor. This paper shows examples of audio specific extensions to the processor's instruction set to create a family of AC-3 decoder implementations that meet multiple performance and cost points. How this approach benefits other audio applications is also discussed.
ER  -