DTS Multichannel Audio Decoder On a 24-Bit Fixed-Point Dual-DSP Architecture

Mesarovic VZ, Dokic MV, Rao RK. DTS Multichannel Audio Decoder On a 24-Bit Fixed-Point Dual-DSP Architecture. In: AES Convention 106. Audio Engineering Society; 1999. Paper 4964. Available from: https://aes.org/publications/elibrary-page/?id=8216

@inproceedings{Mesarovic1999_8216,
  author = {Mesarovic, Vladimir Z. and Dokic, Miroslav V. and Rao, Raghunath K.},
  title = {{DTS Multichannel Audio Decoder On a 24-Bit Fixed-Point Dual-DSP Architecture}},
  booktitle = {AES Convention 106},
  note = {Paper 4964},
  year = {1999},
  month = may,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=8216}
}

TY  - CPAPER
TI  - DTS Multichannel Audio Decoder On a 24-Bit Fixed-Point Dual-DSP Architecture
AU  - Mesarovic, Vladimir Z.
AU  - Dokic, Miroslav V.
AU  - Rao, Raghunath K.
T2  - AES Convention 106
M1  - Paper 4964
PY  - 1999
DA  - 1999/05/06
UR  - https://aes.org/publications/elibrary-page/?id=8216
PB  - Audio Engineering Society
LA  - en
AB  - The Digital Theater Systems (DTS) multichannel film and audio format is becoming a-must-have in today's audio/video receiver and DVD markets. A cost effective IC implementation of this format is very difficult, due to its high computational and memory requirements. We present a cost-effective implementation of DTS decompression algorithm based on a single-die, 24-bit arithmetic, fixed-point, dual-DSP chip. Our flexible architecture presents a significant cost-reduction over existing 32-bit floating-point single-DSP DTS implementations.
ER  -