Theory and VLSI Architectures for Asynchronous Sample-Rate Converters

Adams R, Kwan T. Theory and VLSI Architectures for Asynchronous Sample-Rate Converters. J Audio Eng Soc. 1993;41(7/8):539-555. Available from: https://aes.org/publications/elibrary-page/?id=6993

@article{Adams1993_6993,
  author = {Adams, Robert and Kwan, Tom},
  title = {{Theory and VLSI Architectures for Asynchronous Sample-Rate Converters}},
  journal = {Journal of the Audio Engineering Society},
  volume = {41},
  number = {7/8},
  pages = {539--555},
  year = {1993},
  month = jul,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=6993}
}

TY  - JOUR
TI  - Theory and VLSI Architectures for Asynchronous Sample-Rate Converters
AU  - Adams, Robert
AU  - Kwan, Tom
T2  - Journal of the Audio Engineering Society
J2  - J. Audio Eng. Soc.
VL  - 41
IS  - 7/8
SP  - 539
EP  - 555
PY  - 1993
DA  - 1993/07/06
UR  - https://aes.org/publications/elibrary-page/?id=6993
PB  - Audio Engineering Society
LA  - en
AB  - The theory of asynchronous sample-rate conversion is presented using both the highly interpolated signal-processing model as well as the polyphase filter model. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the correct polyphase filter for each sampling instant. The proposed signal-processing algorithm has been implemented in an all-digital VLSI chip. Measurement results show good agreement with theory.
ER  -