VLSI Architectures for Asynchronous Sample-Rate Conversion

Adams R, Kwan T. VLSI Architectures for Asynchronous Sample-Rate Conversion. In: AES Convention 93. Audio Engineering Society; 1992. Paper 3355. Available from: https://aes.org/publications/elibrary-page/?id=6778

@inproceedings{Adams1992_6778,
  author = {Adams, Robert and Kwan, Tom},
  title = {{VLSI Architectures for Asynchronous Sample-Rate Conversion}},
  booktitle = {AES Convention 93},
  note = {Paper 3355},
  year = {1992},
  month = oct,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=6778}
}

TY  - CPAPER
TI  - VLSI Architectures for Asynchronous Sample-Rate Conversion
AU  - Adams, Robert
AU  - Kwan, Tom
T2  - AES Convention 93
M1  - Paper 3355
PY  - 1992
DA  - 1992/10/06
UR  - https://aes.org/publications/elibrary-page/?id=6778
PB  - Audio Engineering Society
LA  - en
AB  - The theory of asynchronous sample-rate conversion is presented using both the highly-interpolated signal-processing model as well as the polyphase filter model. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the current polyphase filter for each sampling instant. The proposed signal-processing algorithm is well-suited to VLSI implementation, with only modest amounts of RAM, ROM, and digital filter hardware required.
ER  -