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Convention Paper

Jitter Analysis of Asynchronous Sample-Rate Conversion

Authors: Adams, Robert

AES Convention 95 · Paper 3712 · October 1993

Abstract

Jitter has become a major limiting factor in the quality of D/A conversion. The extensive use of serial communications protocols forces the use of PLL-based clock recovery circuits which often produce unacceptable amounts of jitter. The sensitivity of various D/A conversion techniques to jitter varies widely and is often signal dependent. A new VLSI chip has been designed to solve the problem of asynchronous rate conversion between arbitrary frequencies. A servo-control loop with very long time constants has the effect of heavily low-pass filtering the jitter spectrum, which largely eliminates the effects of jitter on signal quality.

Details

Published in
AES Convention 95
AES Convention
95
Paper number
3712
Publication date
October 6, 1993
Session subject
DSP Theory and Applications
Affiliation
Analog Devices Semiconductor, Wilmington, MA (See document for exact affiliation information.)
Type
Convention Paper