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A novel Sigma-Delta based audio DAC system is presented. The converter operates at only 32-times oversampling (1.4 MHz) and uses an eighth-order Sigma-Delta modulator implemented in a single FPGA circuit. Two different DAC circuits have been implemented: One using switched capacitor charge packets and one using nonreturn to zero pulses. A voltage-controlled Xtal oscillator-based PLL ensures low-jitter sampling clock recovery.
Author (s): Risbo, Lars;
Affiliation:
Electronics Institute, Technical University of Denmark, Denmark
(See document for exact affiliation information.)
AES Convention: 96
Paper Number:3808
Publication Date:
1994-02-06
Session subject:
Implementation of Digital Audio Systems
DOI:
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Risbo, Lars; 1994; Field-Programmable Gate-Array-Based 32-Times Oversampling Eighth-Order Sigma-Delta Audio DAC [PDF]; Electronics Institute, Technical University of Denmark, Denmark; Paper 3808; Available from: https://aes.org/publications/elibrary-page/?id=6424
Risbo, Lars; Field-Programmable Gate-Array-Based 32-Times Oversampling Eighth-Order Sigma-Delta Audio DAC [PDF]; Electronics Institute, Technical University of Denmark, Denmark; Paper 3808; 1994 Available: https://aes.org/publications/elibrary-page/?id=6424
@inproceedings{Risbo1994field-programmable,
title={{Field-Programmable Gate-Array-Based 32-Times Oversampling Eighth-Order Sigma-Delta Audio DAC}},
author={Risbo, Lars},
year={1994},
month={feb},
booktitle={Journal of the Audio Engineering Society},
publisher={Paper 3808; AES Convention 96; February 1994},
number={3808},
organization={AES},
}
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