High-Performance Jitter-Reduction Circuit for Digital Audio

Wong WK. High-Performance Jitter-Reduction Circuit for Digital Audio. In: AES Convention 97. Audio Engineering Society; 1994. Paper 3888. Available from: https://aes.org/publications/elibrary-page/?id=6344

@inproceedings{Wong1994_6344,
  author = {Wong, Wai-Ki},
  title = {{High-Performance Jitter-Reduction Circuit for Digital Audio}},
  booktitle = {AES Convention 97},
  note = {Paper 3888},
  year = {1994},
  month = nov,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=6344}
}

TY  - CPAPER
TI  - High-Performance Jitter-Reduction Circuit for Digital Audio
AU  - Wong, Wai-Ki
T2  - AES Convention 97
M1  - Paper 3888
PY  - 1994
DA  - 1994/11/06
UR  - https://aes.org/publications/elibrary-page/?id=6344
PB  - Audio Engineering Society
LA  - en
AB  - A high-performance jitter-reduction circuit based on high-order phase-locked-loop technique has been built for digital audio. It provides over 40-dB attenuation for midfrequencies but still maintains over 10-Hz cutoff frequency. By employing a crystal-based voltage-controlled oscillator, very low intrinsic jitter is achieved.
ER  -