VLSI Implementation of a One-Stage 64:1 FIR Decimator

Andreas D. VLSI Implementation of a One-Stage 64:1 FIR Decimator. In: AES Convention 89. Audio Engineering Society; 1990.pp. 2976:1-12. Available from: https://aes.org/publications/elibrary-page/?id=5717

@inproceedings{Andreas1990_5717,
  author = {Andreas, David},
  title = {{VLSI Implementation of a One-Stage 64:1 FIR Decimator}},
  booktitle = {AES Convention 89},
  pages = {2976:1-12},
  url = {https://aes.org/publications/elibrary-page/?id=5717},
  year = {1990},
  month = sep,
  publisher = {Audio Engineering Society}
}

TY  - CPAPER
TI  - VLSI Implementation of a One-Stage 64:1 FIR Decimator
AU  - Andreas, David
T2  - AES Convention 89
SP  - 1
EP  - 12
M1  - Paper 2976
PY  - 1990
DA  - 1990/09/06
UR  - https://aes.org/publications/elibrary-page/?id=5717
PB  - Audio Engineering Society
LA  - en
AB  - Commercially available Delta-Sigma A/D converters decimate a high-rate input signal in multiple steps using several moving average type FIRs. A stereo digital Decimator Chip has been designed and fabricated which reduces the sample rate of a 1 bit input signal by a factor of 64 in one stage, using a 4096 tap lowpass FIR. The chip has been fabricated in 1.6u CMOS, having a die size of 210mil x 262mil (excluding scribe area), and is capable of running at input sample rates up to 3.6mhz. The internal logic of the VLSI is discussed.
ER  -