FPGA-Based Acceleration of FDTD Sound Field Rendering

Tan Y, Imamura T, Kondo M. FPGA-Based Acceleration of FDTD Sound Field Rendering. J Audio Eng Soc. 2021;69(7/8):542-556. doi:10.17743/jaes.2021.0025

@article{Tan2021_21121,
  author = {Tan, Yiyu and Imamura, Toshiyuki and Kondo, Masaaki},
  title = {{FPGA-Based Acceleration of FDTD Sound Field Rendering}},
  journal = {Journal of the Audio Engineering Society},
  volume = {69},
  number = {7/8},
  pages = {542--556},
  year = {2021},
  month = jul,
  publisher = {Audio Engineering Society},
  doi = {10.17743/jaes.2021.0025},
  url = {https://doi.org/10.17743/jaes.2021.0025}
}

TY  - JOUR
TI  - FPGA-Based Acceleration of FDTD Sound Field Rendering
AU  - Tan, Yiyu
AU  - Imamura, Toshiyuki
AU  - Kondo, Masaaki
T2  - Journal of the Audio Engineering Society
J2  - J. Audio Eng. Soc.
VL  - 69
IS  - 7/8
SP  - 542
EP  - 556
PY  - 2021
DA  - 2021/07/06
DO  - 10.17743/jaes.2021.0025
UR  - https://doi.org/10.17743/jaes.2021.0025
PB  - Audio Engineering Society
LA  - en
AB  - Sound field rendering is computation-intensive and memory-intensive. This research investigates an FPGA-based accelerator for sound field rendering with an FDTD scheme, in which wave equations are directly implemented by reconfigurable hardware, and spatial blocking is applied to alleviate the memory bandwidth requirement. Compared to software simulation performed on a desktop machine with 128 GB DDR4 RAMs and an Intel i7-7820X processor running at 3.6 GHz, the proposed FPGA-based accelerator achieves up to 2.98 times more in computing performance in the case of different layer sizes and different numbers of nodes computed in parallel even though the FPGA system runs at about 267 MHz.
ER  -