Graphical Development Design for a Heterogeneous DSP Core Architecture

Chavez M. Graphical Development Design for a Heterogeneous DSP Core Architecture. In: AES Convention 144. Audio Engineering Society; 2018.pp. 423:1-. Available from: https://aes.org/publications/elibrary-page/?id=19536

@inproceedings{Chavez2018_19536,
  author = {Chavez, Miguel},
  title = {{Graphical Development Design for a Heterogeneous DSP Core Architecture}},
  booktitle = {AES Convention 144},
  pages = {423:1-},
  year = {2018},
  month = may,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=19536}
}

TY  - CPAPER
TI  - Graphical Development Design for a Heterogeneous DSP Core Architecture
AU  - Chavez, Miguel
T2  - AES Convention 144
SP  - 1
M1  - Paper 423
PY  - 2018
DA  - 2018/05/06
UR  - https://aes.org/publications/elibrary-page/?id=19536
PB  - Audio Engineering Society
LA  - en
AB  - For over 15 years, Analog Devices has continued improving its graphical programming environment to support several, audio specific and general purpose digital signal processors (DSPs). As of 2016, all supported processors have either contained single or dual DSP cores whereas both of them have had the same architecture. With the need to have a heterogeneous DSP architecture the team had the challenge to program both cores within the same environment. This paper describes challenges, trade-offs and design decisions made when programming a new heterogeneous DSP core architecture.
ER  -