Efficient Design of a Parallel Graphic Equalizer

Bank B, Belloch JA, Välimäki V. Efficient Design of a Parallel Graphic Equalizer. J Audio Eng Soc. 2017;65(10):817-825. doi:10.17743/jaes.2017.0029

@article{Bank2017_19355,
  author = {Bank, Balázs and Belloch, Jose A. and Välimäki, Vesa},
  title = {{Efficient Design of a Parallel Graphic Equalizer}},
  journal = {Journal of the Audio Engineering Society},
  volume = {65},
  number = {10},
  pages = {817--825},
  year = {2017},
  month = oct,
  publisher = {Audio Engineering Society},
  doi = {10.17743/jaes.2017.0029},
  url = {https://doi.org/10.17743/jaes.2017.0029}
}

TY  - JOUR
TI  - Efficient Design of a Parallel Graphic Equalizer
AU  - Bank, Balázs
AU  - Belloch, Jose A.
AU  - Välimäki, Vesa
T2  - Journal of the Audio Engineering Society
J2  - J. Audio Eng. Soc.
VL  - 65
IS  - 10
SP  - 817
EP  - 825
PY  - 2017
DA  - 2017/10/06
DO  - 10.17743/jaes.2017.0029
UR  - https://doi.org/10.17743/jaes.2017.0029
PB  - Audio Engineering Society
LA  - en
AB  - Accurate design of a parallel graphic equalizer involves the construction of a complex target frequency response, which is obtained by smoothly interpolating using minimum-phase characteristics between defined gains, which is then followed by a least-squares filter design. This work proposes two methods to simplify the design computations. First, the magnitude and phase response of the target is computed as a combination of minimum phase basis functions, which leads to the easier evaluation of the total frequency response. Second, the matrix is decomposed into the product of an orthogonal matrix Q and an upper triangular matrix R, which simplifies the required matrix inversion. A comparison with the previous method shows that the accuracy of the proposed design method is not significantly compromised. And the computational cost is radically reduced, making the new algorithm highly attractive for interactive audio applications. The method has been tested on an ARM-based system-on-Chip Cortex-A7, which is currently used in many mobile devices. For the weighted parallel equalizer design, the total speedup is a factor of 7. For the more efficient nonweighted designs, the computation of the filter coefficients takes 0:87ms on the ARM-A7 processor (the speedup factor is 300 compared to the original method).
ER  -