R. Bassoli, F. Guanziroli, C. Crippa, and G. Nicollini, “Supply-Feedback Fully-Digital Class D Audio Amplifier Featuring 100 dBA+ SNR and 0.5 W to 1 W Selectable Output Power,” in Proc. AES Convention 135, Oct. 2013, Paper 8968. [Online]. Available: https://aes.org/publications/elibrary-page/?id=17017
Bassoli R, Guanziroli F, Crippa C, Nicollini G. Supply-Feedback Fully-Digital Class D Audio Amplifier Featuring 100 dBA+ SNR and 0.5 W to 1 W Selectable Output Power. In: AES Convention 135. Audio Engineering Society; 2013. Paper 8968. Available from: https://aes.org/publications/elibrary-page/?id=17017
@inproceedings{Bassoli2013_17017,
author = {Bassoli, Rossella and Guanziroli, Federico and Crippa, Carlo and Nicollini, Germano},
title = {{Supply-Feedback Fully-Digital Class D Audio Amplifier Featuring 100 dBA+ SNR and 0.5 W to 1 W Selectable Output Power}},
booktitle = {AES Convention 135},
note = {Paper 8968},
year = {2013},
month = oct,
publisher = {Audio Engineering Society},
url = {https://aes.org/publications/elibrary-page/?id=17017}
}
TY - CPAPER
TI - Supply-Feedback Fully-Digital Class D Audio Amplifier Featuring 100 dBA+ SNR and 0.5 W to 1 W Selectable Output Power
AU - Bassoli, Rossella
AU - Guanziroli, Federico
AU - Crippa, Carlo
AU - Nicollini, Germano
T2 - AES Convention 135
M1 - Paper 8968
PY - 2013
DA - 2013/10/06
UR - https://aes.org/publications/elibrary-page/?id=17017
PB - Audio Engineering Society
LA - en
AB - This paper presents a real-time power supply noise correction technique in a fully-digital class D audio amplifier. The power supply is scaled and applied to a 12-bits Nyquist ADC to modify the amplitude of the Pulse-Width-Modulator reference carrier. An improved supply extrapolation algorithm results to a power supply rejection from one to two orders of magnitude higher than reported implementations. Class D sensitivity to clock jitter is presented. SNR higher than 100dBA have been measured in the presence of both power supply ripple and clock jitter. The PWM and output stage are integrated in the same chip in a 0.13µm digital CMOS technology, whereas an external ADC has been used to demonstrate the validity of the supply-feedback algorithm.
ER -
