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Convention Paper

Evaluation of trr Distorting Effects Reduction in DCI-NPC Multilevel Power Amplifiers by Using SiC Diodes and MOSFET Technologies

Authors: Sala, Vicent; Resano, Jr., Tomas; Romeral, Jose Luis; Moreno, Jose Manuel

AES Convention 133 · Paper 8720 · October 2012

Abstract

In the last decade, the Power Amplifier applications have used multilevel diode-clamped-inverter or neutral-point-clamped (DCI-NPC) topologies to present very low distortion at high power. In these applications a lot of research has been done in order to reduce the sources of distortion in the DCI-NPC topologies. One of the most important sources of distortion, and less studied, is the reverse recovery time (trr) of the clamp diodes and MOSFET parasitic diodes. Today, with the emergence of Silicon Carbide (SiC) technologies, these sources of distortion are minimized. This paper presents a comparative study and evaluation of the distortion generated by different combinations of diodes and MOSFETs with Si and SiC technologies in a DCI-NPC multilevel Power Amplifier in order to reduce the distortions generated by the non-idealities of the semiconductor devices.

Details

Published in
AES Convention 133
AES Convention
133
Paper number
8720
Publication date
October 6, 2012
Session subject
Amplifiers, Transducers, and Equipment
Affiliation
UPC-Universitat Politecnica de Catalunya, Terrassa, Catalunya, Spain (See document for exact affiliation information.)
Type
Convention Paper