Time Domain Performance of Decimation Filter Architectures for High Resolution Sigma Delta Analogue to Digital Conversion

Wang Y, Reiss JD. Time Domain Performance of Decimation Filter Architectures for High Resolution Sigma Delta Analogue to Digital Conversion. In: AES Convention 132. Audio Engineering Society; 2012. Paper 8648. Available from: https://aes.org/publications/elibrary-page/?id=16286

@inproceedings{Wang2012_16286,
  author = {Wang, Yonghao and Reiss, Joshua D.},
  title = {{Time Domain Performance of Decimation Filter Architectures for High Resolution Sigma Delta Analogue to Digital Conversion}},
  booktitle = {AES Convention 132},
  note = {Paper 8648},
  year = {2012},
  month = apr,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=16286}
}

TY  - CPAPER
TI  - Time Domain Performance of Decimation Filter Architectures for High Resolution Sigma Delta Analogue to Digital Conversion
AU  - Wang, Yonghao
AU  - Reiss, Joshua D.
T2  - AES Convention 132
M1  - Paper 8648
PY  - 2012
DA  - 2012/04/06
UR  - https://aes.org/publications/elibrary-page/?id=16286
PB  - Audio Engineering Society
LA  - en
AB  - We present the results of a comparison of different decimation architectures for high resolution sigma delta analogue to digital conversion in terms of passband, transition band performance, simulated signal to noise ratio, and computational cost. In particular, we focus on the comparison of time domain group delay response of different filter architectures including classic multistage FIR, cascaded integrator-comb (CIC) with FIR compensation filters, particularly multistage polyphase IIR filter, cascaded halfband minimum phase FIR filter, and multistage minimum phase FIR filter designs. The analysis shows that the multistage minimum phase FIR filter and multistage polyphase IIR filter are most promising for low group delay audio applications.
ER  -