D. Kim, K. Lee, S. Lee, S. Ryu, and C. Son, “Hardware/Software Co-Design of Multi-Format Audio Decoder,” in Proc. AES Convention 124, May 2008, Paper 7349. [Online]. Available: https://aes.org/publications/elibrary-page/?id=14479
Kim D, Lee K, Lee S, Ryu S, Son C. Hardware/Software Co-Design of Multi-Format Audio Decoder. In: AES Convention 124. Audio Engineering Society; 2008. Paper 7349. Available from: https://aes.org/publications/elibrary-page/?id=14479
@inproceedings{Kim2008_14479,
author = {Kim, DoHyung and Lee, KangEun and Lee, Shihwa and Ryu, Soojung and Son, ChangYong},
title = {{Hardware/Software Co-Design of Multi-Format Audio Decoder}},
booktitle = {AES Convention 124},
note = {Paper 7349},
year = {2008},
month = may,
publisher = {Audio Engineering Society},
url = {https://aes.org/publications/elibrary-page/?id=14479}
}
TY - CPAPER
TI - Hardware/Software Co-Design of Multi-Format Audio Decoder
AU - Kim, DoHyung
AU - Lee, KangEun
AU - Lee, Shihwa
AU - Ryu, Soojung
AU - Son, ChangYong
T2 - AES Convention 124
M1 - Paper 7349
PY - 2008
DA - 2008/05/06
UR - https://aes.org/publications/elibrary-page/?id=14479
PB - Audio Engineering Society
LA - en
AB - This paper presents a hardware/software co-design method for the implementation of multi-format audio decoder with ultra low power, small chip size, and high flexibility which are most critical factors in embedded devices. This approach can provide both flexibility and low power with high performance in such a way that hardware implementation has been focused on the commonly used critical blocks of multiple audio decoders having intensive computations. Hardware blocks are well modularized to allow easy and rapid architecture exploration of several digital audio standards. The proposed system can decode MP3 bitstream using only about 4MHz clock frequency and AAC bitstream using only about 7MHz clock frequency on average at the sampling rate of 48 kHz and the target bitrate of 128kbps/stereo.
ER -