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Convention Paper

A 216 kHz 124 dB Single Die Stereo Delta Sigma Audio Analog-to-Digital Converter

Authors: Yang, YuQing; Sculley, Terry; Abraham, Jacob

AES Convention 123 · Paper 7289 · October 2007

Abstract

A 216kHz single die stereo delta sigma ADC is designed for high precision audio applications. A single loop, fifth-order, thirty-three level delta sigma analog modulator with positive and negative feedforward path is implemented. An interpolated multilevel quantizer with unevenly weighted quantization levels replaces a conventional 5-bit flash type quantizer in this design. These new techniques suppress the signal dependent energy inside the delta sigma loop and reduce internal channel noise coupling. Integrated with an on-chip bandgap reference circuit, DEM(dynamic element matching) circuit and a linear phase, FIR decimation filter, the ADC achieves 124dB dynamic range (A-weighted), –110dB THD+N over a 20kHz bandwidth. Inter-channel isolation is 130dB. Power consumption is approximately 330mW

Details

Published in
AES Convention 123
AES Convention
123
Paper number
7289
Publication date
October 6, 2007
Session subject
Signal Processing
Affiliation
Texas Instruments, Inc. (See document for exact affiliation information.)
Type
Convention Paper