Dual Channel Audio Decoding Architecture of Digital TV SoC

Kim HJ, Lee JI, Hwang TH, Lee MH, Moon JH, Oh HO, Choi SJ. Dual Channel Audio Decoding Architecture of Digital TV SoC. In: AES Conference: 29th International Conference: Audio for Mobile and Handheld Devices. Audio Engineering Society; 2006. Paper P-1. Available from: https://aes.org/publications/elibrary-page/?id=13876

@inproceedings{Kim2006_13876,
  author = {Kim, H. J. and Lee, J. I. and Hwang, T. H. and Lee, M. H. and Moon, J. H. and Oh, H. O. and Choi, S. J.},
  title = {{Dual Channel Audio Decoding Architecture of Digital TV SoC}},
  booktitle = {AES Conference: 29th International Conference: Audio for Mobile and Handheld Devices},
  note = {Paper P-1},
  year = {2006},
  month = sep,
  publisher = {Audio Engineering Society},
  url = {https://aes.org/publications/elibrary-page/?id=13876}
}

TY  - CPAPER
TI  - Dual Channel Audio Decoding Architecture of Digital TV SoC
AU  - Kim, H. J.
AU  - Lee, J. I.
AU  - Hwang, T. H.
AU  - Lee, M. H.
AU  - Moon, J. H.
AU  - Oh, H. O.
AU  - Choi, S. J.
T2  - AES Conference: 29th International Conference: Audio for Mobile and Handheld Devices
M1  - Paper P-1
PY  - 2006
DA  - 2006/09/06
UR  - https://aes.org/publications/elibrary-page/?id=13876
PB  - Audio Engineering Society
LA  - en
AB  - In this paper, we describe design issues of an audio decoding processor that can be applied especially to decoding and/or encoding more than two audio contents simultaneously. The dual channel decoding is an emerging issue in the upcoming convergent multimedia applications including Digital TV, DVD, cellular phone, and Internet audio. To satisfy various requirements for dual channel decoding, we propose a novel DSP hardware architecture and a software structure. Keywords: Dual channel decoding, DSP, SoC, Dual CPU, Digital TV.
ER  -